As well known to those skilled in the art, along with progressive miniaturization of semiconductor devices, fine wiring patterns of the semiconductor device are processed by various etching techniques. Generally, the etching techniques are divided two types, i.e., a wet etching and a dry etching. The wet etching has been applied to LSI (Large Scale Integration) devices, in which the widths of the lines of the devices are approximately several μms to several tens of μms. However, since there is a limit to the isotropic wet etching, VLSI (Very Large Scale Integration) devices and ULSI (Ultra Large Scale Integration) devices have been formed by the dry etching, which is capable of an anisotropic etching.
The dry etching techniques are divided into three kinds, i.e., a Chemical Reaction etching, a Physical etching, and an Ion Assisted Etching. In the chemical reaction etching, radicals in a plasma state are generated and react with an “etch object”, which is an object to be etched, thereby performing an etching action. In the physical etching, ions are accelerated and the accelerated ions are physically bombarded with an etch object, thereby performing an etching action. Finally, in the ion assisted etching, an etching action generated by the radicals is assisted by the energy given by the ion bombardment.
Thin films deposited on the VLSI device are an oxide (SiO2) layer, a poly-silicon (Si) layer, a tungsten silicide (WSix) layer, a nitride (Si3N4) layer, an aluminum (Al) layer, a tungsten (W) layer, etc. For the purpose of satisfying both an anisotropic characteristic other than an isotropic characteristic of the etching, and etching selectivity according to the miniaturization and the high integration of the device, these thin films are etching by using plasma, thereby forming wirings and holes on the device.
FIG. 1 shows a conventional dry etching method using plasma. An electric field or an electromagnetic field is induced between two electrodes such as an anode 100 and a cathode 200. Thereby, plasma P is generated above the upper surface of a wafer 300. Then, materials deposited on the upper surface of the wafer 300 are etched using a photoresist pattern as an etching mask. Herein, in order to optimize the etching condition such as etching rate, etching uniformity, and etching selectivity, the distance between two electrodes 100, 200 is regulated by vertically moving one of two electrodes 100, 200.
However, only the materials deposited only on the upper surface 300a of the edge of the wafer is removed by this conventional dry etching method. Therefore, the problem is that the materials deposited on the side surface 300b and the lower surface 300c of the edge of the wafer 300 are not removed.